1. Field of the Invention
The present invention relates to the field of hardware design and synthesis. More specifically, the present invention relates to a method, apparatus, and system for hardware design and synthesis using a heterogeneous modeling framework.
2. General Background
In recent years, VLSI Hardware Design and Synthesis has been made possible using the Hardware Design Languages (HDL), such as VHDL and VERILOG. HDL languages provide the hardware designer with the following abilities:                Design Entry: Design Entry is the first step taken when a circuit concept is to be realized using computer-aided design tools. Using HDL, Design entry is very much like software design using any high order programming languages. It should be noted that design entry in current HDL-based approaches is non-visual. Current state-of-the-art HDL tools do not allow for Visual Design entry similar to common schematic entry tools such “AUTOCAD”.        Behavior Description: Features of HDL allow electrical aspects of the circuit behavior (such as rise and fall times of signals, delays through gates, and functional operation) to be precisely described. The resulting HDL simulation models can then be used as building blocks in larger circuits (using schematics, block diagrams or system-level HDL descriptions) for the purpose of simulation. When creating a behavioral description of a circuit, HDL allows the designer to describe the circuit in terms of its operation over time.        Design Simulation: HDL provides the designer with the ability to simulate the design. Executing HDL models (programs) result in discrete event simulations of the digital circuits that are being designed.        
Structure Description: HDL allows the designer to describe the circuit in terms of its components. Structure can be used to create a very low-level description of a circuit (such as a gate-level or transistor-level description) or a very high-level description (such as a block diagram).
While using hardware design languages such as HDL for VLSI hardware design and synthesis has gained popularity, such approaches still have several shortcomings some of which are list below:
                Hardware Design Languages are advanced high order programming languages. They require thorough knowledge and experience in programming techniques and languages. This adds the burden requiring that VLSI hardware designer to be an established programmer who is familiar with advanced programming topics such as Object Oriented programming, Structured Programming, Strong Data Typing, and Component-based Design techniques.        In most VLSI ASIC applications, such as Digital Communication Systems, the algorithms to be implemented in VLSI hardware are initially developed in C, C++, or Java. The syntax of most HDL languages is different than C, C++ or Java. This means that these algorithms have be hand translated by the hardware designer into HDL. Adding yet another burden on the designer not only to learn HDL, but also to be capable of understanding C, C++ or Java.        HDL simulation capabilities are limited to discrete event simulation of digital logic. This is too restrictive in trying to build current VLSI ASIC designs containing mixed signal and analog components. The designer has to use other system modeling techniques (such SMULINK or SPICE) to describe parts of the circuit that are not digital. Adding yet another burden on the hardware designer to acquire and learn other modeling and simulation tools.        State of the art tools in HDL design entry are non-visual, expensive, and have restricted portability to other platforms. Furthermore HDL structural model simulation requires expensive special hardware accelerators.        
Accordingly, there exists a need for a method and system for performing hardware design and synthesis that alleviate the aforementioned shortcomings and provide more versatility to increase the hardware designer productivity.